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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CTIITCTRL, CTI Integration mode Control register</h1><p>The CTIITCTRL characteristics are:</p><h2>Purpose</h2>
        <p>Enables the CTI to switch from its default mode into integration mode, where test software can control directly the inputs and outputs of the PE, for integration testing or topology detection.</p>
      <h2>Configuration</h2><p>The power domain of CTIITCTRL is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.
    </p><p>Implementation of this register is <span class="arm-defined-word">OPTIONAL</span>.</p><h2>Attributes</h2>
        <p>CTIITCTRL is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="31"><a href="#fieldset_0-31_1">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">IME</a></td></tr></tbody></table><h4 id="fieldset_0-31_1">Bits [31:1]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-0_0">IME, bit [0]</h4><div class="field">
      <p>Integration mode enable. When IME == 1, the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p>
    <table class="valuetable"><tr><th>IME</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Normal operation.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Integration mode enabled.</p>
        </td></tr></table><p>The following resets apply:</p><ul>
<li>
<p>If the register is implemented in the Core power domain:</p>
<ul>
<li>
<p>On a Cold reset, this field resets to 0.</p>

</li><li>
<p>On an External debug reset, the value of this field is unchanged.</p>

</li><li>
<p>On a Warm reset, the value of this field is unchanged.</p>

</li></ul>

</li><li>
<p>If the register is implemented in the External debug power domain:</p>
<ul>
<li>
<p>On a Cold reset, the value of this field is unchanged.</p>

</li><li>
<p>On an External debug reset, this field resets to 0.</p>

</li><li>
<p>On a Warm reset, the value of this field is unchanged.</p>

</li></ul>

</li></ul></div><h2>Accessing CTIITCTRL</h2><h4>CTIITCTRL can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>CTI</td><td><span class="hexnumber">0xF00</span></td><td>CTIITCTRL</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus(), accesses to this register are <span class="access_level">RO</span>.
          </li><li>When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus(), accesses to this register are <span class="access_level">RW</span>.
          </li><li>Otherwise, accesses to this register are <span class="access_level">IMPDEF</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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